1. Field of Invention
The present invention relates to field-effect transistors (FETs), and more especially to MOSFETs (metal oxide semiconductor field effect transistors). More particularly, the invention involves an FET device having an integrated Schottky diode connected between its bulk terminal and its drain or source terminal.
2. Description of Related Art
One important problem with MOSFETs is that, under some operating conditions, a variety of reasons may cause one or more terminals of a MOSFET to experience excessive voltage. One of these reasons, for example, is capacitive coupling. To illustrate how a typical MOSFET may experience excessive voltage due to capacitive coupling, cross-sections of a p-channel MOSFET 100 and an n-channel MOSFET 125 are shown in FIG. 1.
The p-channel MOSFET 100 is formed in an n-well 101 located in a p-type silicon substrate 102; the substrate 102 may also be referred to as a "wafer." The n-channel MOSFET 125 is formed in the p-type silicon substrate 102. The term "bulk terminal" will be used herein to refer to the silicon structure upon which a MOSFET is formed, that is, an n-well or an n-type substrate in the case of a p-channel MOSFET, or a p-well or a p-type substrate in the case of an n-channel MOSFET. Thus, the bulk terminal of the MOSFET 100 is the n-well 101, and the bulk terminal of the MOSFET 125 is the p-type silicon substrate 102.
The MOSFET 100 has a source 103, a gate 104, and a drain 105. The source 103 is formed by a p+ region 106 located beneath a layer of metal-silicide 108 made from silicon combined with a refractory metal such as titanium, platinum, cobalt, or the like. The drain 105 is also formed by a p+ region 110 located beneath a layer of metal-silicide 112. The gate 104 includes a layer of p+ or n+ doped polycrystalline silicon 114 clad with a layer of metal-silicide 116. The MOSFET 100 also includes a biasing region 120, which is used in supplying a bias voltage to the n-well 101. The biasing region 120 includes an n+ region 122 underlying a layer of metal-silicide 124.
As mentioned above, the n-channel MOSFET 125 is formed in the p-type silicon substrate 102. The MOSFET 125 has a source 126, a gate 128, and a drain 130. The source 126 is formed by an n+ region 132 located beneath a layer of metal-silicide 134. Similarly, the drain 130 is formed by an n+ region 136 located beneath a layer of metal-silicide 138. The gate 128 includes a layer of p+ or n+ doped polycrystalline silicon 140 clad with a layer of metal-silicide 142. The oxide layer 118 separates the gate 128 from the p-type substrate 102.
A layer of oxide 118 separates the gates 104 and 128 from the n-well 101 and the p-type substrate 102, respectively. The oxide layer 118 includes thickened field isolation regions 118a and thin regions 118b. The field isolation regions 118a insulate the MOSFET 100, the MOSFET 125, and the biasing region 120 from each other, as well as from other MOSFETs (not shown) located on the p-type substrate 102.
The structure of the MOSFET 100 is more easily understood by considering the schematic representation of FIG. 2A. The MOSFET 100 includes a diode 220 to represent the p-n junction diode formed by the p+ region 110 and the n-well 101. If the voltage at the drain 105 rises to a certain level, the diode 220 turns on, and current flows from the p+ region 110 to the n-well 101. In the schematic representation of FIG. 2A, current flows from the drain 105 through the diode 220. The turn-on voltage of the diode 220 is assumed to be 0.7 V, which is the typical turn-on voltage of most silicon p-n junction diodes. The maximum voltage at the drain 105 is therefore V.sub.dd plus 0.7 V. When the source 103 and the n-well 101 are both connected to V.sub.dd, the diode 220 will effectively limit V.sub.ds to 0.7 V above V.sub.dd.
Operation of the MOSFETs 100, 125 is further explained by considering the operation of an inverter constructed with the MOSFETs 100, 125. An inverter provides an illustrative example because it is a common application of MOSFETs such as the MOSFETs 100, 125. Referring to FIG. 2, the inverter is schematically represented by an inverter-model 200 that includes the MOSFETs 100, 125, along with various circuit components 220, 221, 222, and 224 to simulate various electrical characteristics of the MOSFETs 100, 125.
The inverter-model 200 is constructed by electrically connecting the drain 130 to the drain 105. The source 103 is electrically connected to V.sub.dd, which provides a power supply voltage such as 3.3 V to the circuit. The n-well 101 is also connected to V.sub.dd (connection not shown). The source 126 is electrically connected to V.sub.ss, which is grounded; the substrate 102 is also connected to V.sub.ss (connection not shown). The input to the inverter-model 200 is electrically connected to the gates 104, 128, and the output of the inverter-model 200 appears on a node 218.
The inverter-model 200 includes the diode 220, which represents the p-n junction diode formed by the p+ region 110 and the n-well 101, as explained above. If the voltage at the drain 130 rises to 0.7 V, the diode 220 turns on, and current flows from the node 218 through the diode 220. The maximum voltage at the node 218 is therefore V.sub.dd plus 0.7 V.
The inverter-model 200 also includes a diode 221 to represent the p-n junction diode formed by the p-type substrate 102 and the n+ region 136. If the voltage at the node 218 falls to a certain level, the diode 221 turns on, and current flows from the p-type substrate 102 to the n+ region 136. In the schematic representation of FIG. 2, current flows from V.sub.ss through the diode 221, thereby limiting the voltage drop at the node 218. The voltage of the node 218 is limited to 0.7 V below V.sub.ss, assuming that the turn-on voltage of the diode 221 is 0.7 V.
As explained above, the p-n junction diodes 220, 221 of the inverter-model 200 are actually part of the drains 105, 130. The sources 103, 126 additionally include p-n junction diodes (not shown), wherein one diode is formed between the p+ region 106 and the n-well 101, and the other diode is formed between the n+ region 132 and the p-type substrate 102. These additional diodes are not discussed herein, however, since they are inoperative when the MOSFETs 100, 125 are configured like the inverter of FIG. 2. They are inoperative because both diodes are effectively shorted out. For example, the p-n junction diode associated with the source 103 is inoperative since both the n-well 101 and the source 103 are connected to V.sub.dd.
The inverter-model 200 also includes a load capacitor 222, which simulates the capacitance of a load connected to the MOSFETs 100, 125; the capacitor 222 also simulates the self-loading of the MOSFETs 100, 125. Also included is a coupling capacitor 224, to represent the coupling capacitance between the node 218 and an adjacent node 226 on the p-type substrate 102. The adjacent node 226 is provided to simulate the signal produced by another electrical component contained on the p-type substrate 102, such as a nearby current-carrying wire. One of the main reasons to include the node 226 and capacitor 224 is to study the reaction of the inverter-model 200 when the node 226 experiences a transition from a low voltage to a high voltage.
If the node 226 undergoes a low-to-high transition while the node 218 is charged to V.sub.dd, the capacitor 224 transfers charge to the node 218, due to "capacitive coupling." The voltage increase at the node 218 depends upon the amount of the voltage increase at the node 226, as well as the ratio of the capacitor 224 to the total capacitance of the capacitors 222, 224. For example, if the ratio between the capacitor 224 and the total capacitance of the capacitors 222, 224 is 0.2, and the voltage at the node 226 increases from 0 to V.sub.dd, then the voltage at the node 218 will exceed V.sub.dd by 0.2(V.sub.dd), i.e. node 218 will experience 1.2(V.sub.dd).
To illustrate this further, an example will be given. Many CMOS (complimentary metal oxide semiconductor) circuits such as microprocessor and memory circuits utilize a V.sub.dd of 3.3 V. If this voltage is supplied within a tolerance of .+-.10%, then it is possible that V.sub.dd may be as high as 3.6 V. If V.sub.dd is 3.6 V, and the ratio of the capacitor 224 to the total capacitance 222, 224 is 0.2, then the voltage at the node 104 will increase to 1.2(3.6)=4.32 V, which exceeds V.sub.dd by 0.72 V. This excess voltage cannot go above 0.7 V, however, due to the clamping action of the diode 220. Specifically, if the voltage at the node 218 exceeds V.sub.dd by 0.7 V, then the diode 220 lowers the voltage at the node 218 by turning on and conducting current from the node 218 to V.sub.dd. Since the source 103 is also electrically connected to V.sub.dd, the drain-source voltage (V.sub.ds) of the MOSFET 100 is therefore effectively clamped to 0.7 V.
Excess voltage in MOS circuits can lead to a variety of deleterious effects, such as increased off current, "punch-through", and "snapback". Moreover, excess voltage may increase the circuit's susceptibility to wearout, due to phenomena such as "time dependent dielectric breakdown" or "hot carrier degradation". For ease of explanation, increased susceptibility to wearout due to hot carrier degradation will be discussed herein as a representative example of the deleterious effects of excess voltage; it is understood that other phenomena are similarly affected by excess voltage. Hot carrier wearout is discussed in C. Hu et al, "Hot-Electron-Induced MOSFET Degradation--Model, Monitor, Improvement," IEEE Journal of Solid-State Circuits, Vol SC-20, No. 1, February 1986, pp. 295-305.
The hot carrier wearout problem is graphically depicted in FIG. 3, wherein the vertical axis represents "useful lifetime" of a MOSFET in years and the horizontal axis shows the inverse of the MOSFET's V.sub.ds. The useful lifetime is the time for which the MOSFET can be operated before wearout causes a significant drift in the operating parameters of the MOSFET. From FIG. 3, it can be seen that the lifetime of a MOSFET significantly decreases for larger values of V.sub.ds. For example, an increase in V.sub.ds from 3.6 V to 4.3 V can reduce useful lifetime from 730 years to 8.7 years.
One of the limitations faced by MOSFET circuit designers is that Wearout problems are exacerbated when the size of a circuit is decreased, since decreasing the circuit size effectively increases the electric fields experienced by the circuit. Accordingly, one approach used to combat wearout problems in MOSFETs is to reduce the power supply voltage. Although this approach might be satisfactory in some applications, it is limited since it causes reduced circuit performance, such as decreased operating speed.
Another approach seeks to reduce electric fields in MOSFETs by using lightly doped drain (LDD) structures. This is discussed in J. Sanchez et al., "Drain-Engineered Hot-Electron-Resistant Device Structures: A Review," IEEE Transactions on Electrical Devices, ED-36, June 1989. Although the use of LDD structures might be beneficial in some applications, circuit performance is typically reduced. Moreover, LDD structures require significantly more complicated manufacturing processes.
It would be beneficial, then, to have a new MOSFET with improved wearout reliability, that retains desirable features such as compatibility with standard supply voltages and small circuit dimensions. Moreover, it would be advantageous if such a MOSFET did not require a more complicated manufacturing process.
The manufacturing or "fabrication" process for producing MOSFETs such as the MOSFETs 100, 125 is already established in the art. FIGS. 3A-3F depict the steps involved in this process, as applied to the construction of the p-channel MOSFET 100 and the n-channel MOSFET 125. Referring to FIG. 3A, the n-well 101 is first created by using ion implantation to dope part of the substrate 102. Then, the oxide layer 118 is created; first, an oxide layer of even thickness (not shown) is grown, then selected areas 304, 306, 308 of the oxide layer are thickened; these thicker areas are called "field isolation regions." The field isolation regions 304, 306, 308 provide insulation between adjacent MOSFETs; for example, the region 306 insulates the MOSFETs 100, 125. The areas 300, 302 are not thickened since silicon nitride (Si.sub.3 N.sub.4) is deposited over the areas 300, 302 prior to growing more oxide. Where the oxide is not covered by silicon nitride, the oxide thickens and "balloons" to form the field isolation regions 304,306, 308. The silicon nitride is then chemically removed, as is the oxide in the regions 300, 302. Finally, a new thin oxide is grown in the regions 300, 302.
Next, the gates 104, 128 are constructed by (1) depositing and etching layers of polycrystalline silicon 114, 140; (2) depositing a metal layer (not shown); and (3) forming the metal-silicide layers 134, 142, 138, 108, 116, and 110 (FIG. 3B) by reacting the metal with silicon in a procedure such as annealing. Then, the p+ regions 106, 110 (FIG. 3C) and the n+ regions 132, 136 (FIG. 3D) are doped using p+ and n+ ion implantation, respectively. During implantation of the p+ regions 106, 110, an implant mask 310 having an aperture 312 is Used as a template to selectively confine p+ ion implantation to the area 302 (FIG. 3E). Similarly, during implantation of the n+ regions 132, 136 an implant mask 314 having an aperture 316 is used to confine n+ ion implantation to the area 302 (FIG. 3F).